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СMS EMU Track Finder - 2010 - see for more detail review.

Self Trigger-ATLAS - 2010 - see for more detail review.

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Of "СMS EMU Track Finder - 2009" review see: СMS EMU Track Finder - 2009 (see Fig. 1)

Of "Self Trigger-ATLAS - 2009" review see: Self Trigger-ATLAS - 2009 (see Fig. 2)

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     The Track-Finder is implemented as 12 sector processors, which identify up to three best muons in 60⁰ azimuthal sectors. The track-finding algorithms are inherently 3-dimentional to achieve maximum background rejection. The purpose of the CSC track-finding processor is to link trigger primitives (track segments) from individual muon stations into complete tracks, measure the transverse momentum p _t from the sagitta induced by the magnetic bending, and report the number and quality of tracks to the Level-1 global trigger.

     The block diagram of track-finding processor is shown in Fig.3. The input of processor is capable of collecting track segments from multiple bunch crossings. The bunch crossing analyzer accumulates track segments for a couple of BX to accommodate error in BX. The extrapolation units take information from two track segments in different stations, and tests if those two segments are compatible with the muon originating from the nominal collision vertex with a curvature consistent with the magnetic bending in that region. The track assembler units examine the output of extrapolation units and determines if any track segment pairs belong to the same muon. The final selection unit combines the information from track assembler streams, cancels redundant tracks, and selects the three best distinct tracks. The assignment unit measures the momentum of the identified muons in the final stage of processing. The overall latency of processor is expected to be about.

     The first prototype of processor (Fig.4) has been fabricated in 2000 and successfully tested in 2000 - 2001. This is a 9U VME module 400 mm depth. There are 17 Field Programmable Gate Array (FPGA) chips as core elements of module. The pre-production prototype of processor is under design. The new processor occupies only one big size FPGA chip. It allows reducing the processing time from 375 ns (old design) to 175 ns. It also allows combining three sector receivers and processor on the one board to reduce the total number of modules from 48 to 12. According to schedule the PCB layout of pre-production prototype will be completed by September 2002. The fabrication of pre-production will be finished by November 2002. The testing of pre-production should be done by April 2003.